le16X50UARTSync1: Detected 16550AF/C/CF FIFO=16 MaxBaud=115200
AGP: Found an AGP 3.0 compliant device.
AGP: Chipset is RS300.
AGPATI: map mmio dc100000 to @1a148000
(00)=0000022c   (04)=00000080   (08)=00000308   (0c)=000000c3 
#define MM_INDEX                               0x0000  
#define MM_DATA                                0x0004  
(10)=0000000c   (14)=0128c000   (18)=10040400   (1c)=02010000   
(20)=01000004   (24)=01000001   (28)=00010f00   (2c)=00000000   
(30)=5133a3b0   (34)=84000000   (38)=00010000   (3c)=00010000  
#define BUS_CNTL                               0x0030  
#define BUS_CNTL1                              0x0034
(40)=00000000   (44)=00080007   (48)=00000000   (4c)=00000000   
#define GEN_INT_CNTL                           0x0040  
#define GEN_INT_STATUS                         0x0044  
#define HI_STAT                                0x004C  
(50)=03000600   (54)=00080048   (58)=ff604102   (5c)=00000002 
#define CRTC_GEN_CNTL                          0x0050
#define CRTC_EXT_CNTL                          0x0054
#define DAC_CNTL                               0x0058 
#define CRTC_STATUS                            0x005C  
(60)=00000300   (64)=00000300   (68)=00000300   (6c)=00000300   
#define GPIO_VGA_DDC                           0x0060  
#define GPIO_DVI_DDC                           0x0064  
#define GPIO_MONID                             0x0068  
#define GPIO_CRT2_DDC                          0x006c
(70)=00000000   (74)=00000000   (78)=00000000   (7c)=00000002   
(80)=00000000   (84)=00000000   (88)=00000000   (8c)=00000000   
(90)=00000000   (94)=00000000   (98)=00000000   (9c)=00000000  
#define I2C_CNTL_1			       0x0094  
(a0)=00000000   (a4)=00000000   (a8)=00000000   (ac)=00000000   
(b0)=00000000   (b4)=00000000   (b8)=00401004   (bc)=00000000   
(c0)=00000000   (c4)=00000000   (c8)=00000000   (cc)=00000000  
(d0)=00000000   (d4)=00000000   (d8)=00000000   (dc)=00000000 
(e0)=00010100   (e4)=04120000   (e8)=00000000   (ec)=00004443  
#define RADEON_CONFIG_CNTL                0x00e0
#define RADEON_CONFIG_XSTRAP              0x00e4
#define RADEON_CONFIG_BONDS               0x00e8
(f0)=00000000   (f4)=00000000   (f8)=00700000   (fc)=00000000 
#define RADEON_CONFIG_MEMSIZE            0x00f8
(100)=e4000000   (104)=e6000000   (108)=02000000   (10c)=dc108000
#define RADEON_CONFIG_APER_0_BASE    0x0100
#define RADEON_CONFIG_APER_1_BASE    0x0104
#define RADEON_CONFIG_APER_SIZE      0x0108
#define RADEON_CONFIG_REG_1_BASE     0x010c
(110)=00008000   (114)=00000000   (118)=00187b88   (11c)=80000003 
#define RADEON_CONFIG_REG_APER_SIZE  0x0110
(120)=00000000   (124)=00000000   (128)=00000000   (12c)=00000000  
(130)=70000000   (134)=00000000   (138)=00000000   (13c)=00000000  
#define HOST_PATH_CNTL                         0x0130  
#define HDP_DEBUG                              0x0138  
#define SW_SEMAPHORE                           0x013C
(140)=2a002002   (144)=1305657a   (148)=0fff0e00   (14c)=003f0000  
#define RADEON_MEM_CNTL       		    0x0140
#define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */
#define RADEON_MEM_ADDR_CONFIG  	    0x0148
#define RADEON_MEM_INTF_CNTL                0x014c
(150)=0009000b   (154)=01ffffff   (158)=5060006a   (15c)=0fff0e00   
#define RADEON_MEM_STR_CNTL                 0x0150	//MC_STATUS 
#define RADEON_MEM_INIT_LAT_TIMER           0x0154
#define RADEON_MEM_SDRAM_MODE_REG           0x0158
#define NB_TOM				    0x015c
(160)=00000040   (164)=00000000   (168)=0000001b   (16c)=00000404  
#define PAD_AGPINPUT_DELAY                     0x0164  
#define PAD_CTLR_STRENGTH                      0x0168  
#define PAD_CTLR_UPDATE                        0x016C
(170)=00000000   (174)=00000000   (178)=306009e1   (17c)=86868686  
#define RADEON_AGP_BASE              0x0170
#define RADEON_AGP_CNTL              0x0174
#define MEM_IO_CNTL_A0    	     0x0178  
#define R300_MC_READ_CNTL_AB         0x017c
(180)=00000000   (184)=00400000   (188)=00000000   (18c)=00000000   
#define MEM_IO_CNTL_B0                         0x0180
#define MEM_IO_CNTL_B1                         0x0184
#define MC_DEBUG                               0x0188
#define MEM_IO_OE_CNTL                         0x018C  
(190)=00050000   (194)=00002202   (198)=00000000   (19c)=00000000  

(1a0)=00000000   (1a4)=000007db   (1a8)=00000000   (1ac)=00000000  
(1b0)=00000000   (1b4)=0b00ffff   (1b8)=00000000   (1bc)=00000002   
(1c0)=00ff0000   (1c4)=00000105   (1c8)=00000000   (1cc)=00000000   
(1d0)=00000000   (1d4)=00000004   (1d8)=00000000   (1dc)=00000000  
#define RADEON_AIC_CNTL                     0x01d0
#       define RADEON_PCIGART_TRANSLATE_EN     (1 << 0)
#define RADEON_AIC_LO_ADDR                  0x01dc
//joblo
#define AIC_CTRL                               0x01D0
#define AIC_STAT                               0x01D4
#define AIC_PT_BASE                            0x01D8
#define AIC_LO_ADDR                            0x01DC  
#define AIC_HI_ADDR                            0x01E0  
#define AIC_TLB_ADDR                           0x01E4  
#define AIC_TLB_DATA                           0x01E8  
(1e0)=00000000   (1e4)=00000000   (1e8)=00000000   (1ec)=00000000   
(1f0)=00000000   (1f4)=00000000   (1f8)=00000000   (1fc)=00000000   
(f00)=58351002   (f04)=02b00207   (f08)=03000000   (f0c)=00004210   #define RADEON_COMMAND   0x0f04 /* PCI */
(f10)=e4000008   (f14)=00009001   (f18)=dc100000   (f1c)=00000000   
(f20)=00000000   (f24)=00000000   (f28)=00000000   (f2c)=6102144d   
(f30)=00000000   (f34)=00000058   (f38)=00000000   (f3c)=0008010a   
(f40)=00000000   (f44)=00000000   (f48)=00000000   (f4c)=6102144d   
(f50)=06020001   (f54)=00000000   (f58)=00305002   (f5c)=ff001e3b   
(f60)=00000200   (f64)=00000000   (f68)=00000000   (f6c)=00000000   
(f70)=00000000   (f74)=00000000   (f78)=00000000   (f7c)=00000000   
(f80)=59451002   (f84)=02b00000   (f88)=03800000   (f8c)=00000000   
(f90)=00000008   (f94)=00000000   (f98)=00000000   (f9c)=00000000   
(fa0)=00000000   (fa4)=00000000   (fa8)=00000000   (fac)=6103144d   
(fb0)=00000000   (fb4)=00000050   (fb8)=00000000   (fbc)=000800ff   
(fc0)=00000000   (fc4)=00000000   (fc8)=00000000   (fcc)=00000000   
(fd0)=06020001   (fd4)=00000000   (fd8)=00305002   (fdc)=ff001e3b   
(fe0)=00000200   (fe4)=00000000   (fe8)=00000000   (fec)=00000000   
(ff0)=00000000   (ff4)=00000000   (ff8)=00000000   (ffc)=00000000   
AGP: systemLength	= 04000000
AGPATI: Get BestAPBASE
AGP: VRAM = [e4000000, 04000000]
AGP: gartPhys = 03f33000
AGP: APBASE 00000380
AGPATI: previous att_base 00060000
AGP: gartPhys written 00060000
AGP: Aperture [00000380:04000000]
AGP: Setting 08 data rate
AGPATI Bind memory 024ac000 offset 00000004 -> phys 00503001
AGPATI Bind memory 024ac000 offset 00000008 -> phys 00503001
AGPATI Bind memory 024ac000 offset 0000000c -> phys 00503001
AGPATI Bind memory 024ac000 offset 00000010 -> phys 00503001
ApplePS2Trackpad: Synaptics TouchPad v6.2
IPv6 packet filtering initialized, default to accept, logging disabled
AppleBCM440XEthernet: Ethernet address 00:00:f0:78:c9:b7
